FIG. 1 shows a general scheme of a liquid crystal display (LCD) device for displaying pictures thereon. Referring to FIG. 1, a general function of an LCD controller 14 is transferring contents of a video buffer embedded in a frame memory (or system memory) 12 to a LCD device 16. The LCD device 16 includes a gate driver and a source driver for driving LCD panels, and the LCD controller 14 generates signals to control the drivers. The control signals provided from the LCD controller 14 are generally divided into two types, i.e. clock signals such as pixel clock, line clock, and frame clock for synchronization between two modules, and data signals required for providing picture data to be displayed on LCD panels. In general, the data signals are formed of 4-bit, 8-bit, or 16-bit, which allows a bandwidth of data transferred to a LCD driver to be large.
Further, the LCD controller 14 supports not only white and black mode but also gray levels by use of a dither and frame rate control block. The dither and frame rate control block is used for expressing gray level values as binary data. Suppose that gray level values for 4 gray levels are “0, ⅓, ⅔ and 1”, binary data transferred to the LCD device is “0” or “1”. For the purpose of expressing the gray level values such as “⅓” and “⅔”, binary data is transferred in a certain number of frames such that “0” in a first frame, “1” in a second frame, and “0” in a third frame are respectively transferred. As a result, the transferred data value is “010”, which results in making a duty cycle to be “⅓” which expresses the gray level of “⅓”.
In general, the dither and frame rate control block includes dithering pattern registers to store gray level values and a control unit to control drawing a value for a frame from the registers. However, conventional LCD controllers have more dithering pattern registers than needed to store required gray level values. Specifically, the conventional dithering pattern registers are configured as a 4-bit unit to synchronously provide four (4) pixel values. Such a configuration of the dithering pattern registers forms 4-bit dithering pattern as much as a denominator value to express dithering pattern values for plural gray levels. That is, assuming that a denominator value of a predetermined gray level is “7”, bit length of the dithering pattern registers is 28 (=4×7) bits. If a denominator value of a predetermined gray level is “5”, bit length of the dithering pattern registers is 20 (=4×5) bits. Dithering pattern values of the dithering pattern registers are programmed to have a value as much as a required duty cycle in one bit length. For instance, if the gray level is “{fraction (1/7)}”, the dithering pattern value of a corresponding dithering pattern register is programmed to assign “1” to 4 bits and “0” to the rest (24 bits) of the total 28 bits.
Respective dithering pattern values for 16 gray levels dithered by the foregoing manner are as follows:
{fraction (6/7)}: 0111 1111 1101 1111 1011 1111 1110
⅘: 0111 1110 1011 1101 1111
{fraction (5/7)}: 0111 1011 1110 0101 1101 1011 1110
¾: 0111 1101 1011 1110
⅔: 1101 0110 1011
⅗: 0101 1010 0101 1011 1110
{fraction (4/7)}: 1011 0101 1010 0101 1010 0101 1110
½: 1010 0101 1010 0101
{fraction (3/7)}: 0100 1010 0101 1010 0101 1010 0001
⅖: 1010 0101 1010 0100 0001
⅓: 0010 1001 0100
¼: 1000 0010 0100 0001
⅕: 1000 0001 0100 0010 0000
{fraction (1/7)}: 1000 0000 0010 0000 0100 0000 0001
Thus, the size of the total dithering pattern values in the dithering pattern registers is 292 (=7×4×5+5×4×4+4×4×3+3×4×2) bits. Since circuitry for one bit is made of a flip-flop, the hardware cost for the conventional dithering pattern registers increases due to the large size of the dithering pattern value data. In addition, power consumption of the dithering pattern registers also increases.
Moreover, in the conventional LCD controller, only one nibble is continuously supplied through one line among the respective bit patterns. Assuming that all of a first line of a frame have gray level values of “{fraction (1/7)}”, a specific nibble of the dithering pattern values for the gray level “{fraction (1/7)}” is continuously provided. If only a first nibble of the dithering pattern values for the gray level “{fraction (1/7)}” is selected, data “1000” is always provided in the line. It is temporally possible to make the dithering pattern value for the gray level “{fraction (1/7)}”, but the data “1000” is spatially reiterative in one line. This also occurs in the case of providing the dithering pattern value for the gray level “¼”.